Research Brief

  

Electronically steerable parasitic array radiator (ESPAR) antenna is a novel low-cost technique to gain horizontal diversity while maintaining one RF front-end, low power consumption, and simple wiring at the mobile receiver. Compared with conventional multiple antennas system where each antenna is equipped with one RF front-end hardware set, ESPAR antenna can achieve the similar diversity order to that of multiple antennas but only using one RF front-end hardware set. However, the main drawback of the ESPAR based system is that the channel estimation usually should be realized in time-domain because the received signal for each antenna element or parasitic element will be overlapped each other both in the frequency and time domain. To solve the channel estimation problem, a compressed sensing (CS) based scheme has been proposed. However, it requires a huge computational complexity. In this research, we work on reducing the complexity for the channel estimation in the ESPAR-OFDM system. Moreover, we provide an RTL level hardware architecture and the FPGA implementation for the proposed method.

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